IBM's new computer chips can fit 30 million transistors on your fingertip

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Especially for the latter, which are severely limited by how much silicon can be crammed in such a small space, IBM's 5 nm chips could give the industry the break it needs to become smarter and more capable in powering the smart homes of tomorrow.

Moore's law, coined first in 1970, is the observation that the number of transistors that can be accommodated on a single chip doubles nearly every two years.

"For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential, "said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research".

Science and Engineerings NanoTech Complex in Albany, NY oversee the operation of the EUV lithography tool used in the industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. Not only that, but the 5nm chips also promise a 40% increase in performance or a 75% reduction in power consumption over the 10nm process technology now in use by Samsung.

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Lastly, the Galaxy Note 8 is expected to make its official debut at IFA 2017, which kicks off on September 1 in Berlin. The new 5 inches (12.7 centimetre) and 5.8 inch (14.7 centimetre) iPhone models, will have a wraparound OLED screen.

The 5nm chips will employ the same Extreme Ultraviolet (EUV) lithography used for IBM's 7nm test node chips that the company unveiled in 2015. They have achieved this by venturing further into nanosheet semiconductor technology. Well, 7nm chips can hold 20 billion transistors. If going raw performance route, these 5nm chips can help accelerate cognitive computing efforts, which is a red hot field now.

More details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits Conference in Kyoto, Japan. However, it's also painting a rosy picture for the future of mobile devices - it imagines phones having "two to three times" more battery life than current devices. IBM claims that FinFET could possibly scale down to 5nm, but there's a performance ceiling on that design due to the limits of current flow through the minuscule fins at that scale.

According to the research team, the use of nanosheets allows them to create gate-all-around (GAA) FETs, which are broadly believed to be the most likely follow-up to the FinFET technology cutting-edge silicon designs use today. Instead of having one single vertical fin, the horizontal "stack" can send signals through four gates, providing for better leakage control at smaller scales. Or, more interestingly, up 75 percent power savings at the current generation's level of performance.

As to why developers are making thinner and thinner chips, in the first place, the answer has to do with speed and size.

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